1. Technical Field
The present invention relates to semiconductor memory devices, and more particularly, to a line layout structure of a semiconductor memory device.
2. Discussion of Related Art
Development of semiconductor memory device technologies has lead to high integration, high performance and low cost devices. Corresponding advancements in process techniques have lead to a generalization of multi-layered metal structures. The multi-layered metal structures allow for improved integration of chips but increase process costs. For this reason, memory manufacturers design products having metal structures of reduced size and cost, which may not include the multi-layered metal structures.
Typically, in static random access memories (SRAMs), word lines are formed of polysilicon having desirable resistance. Accordingly, it is common to adopt a structure in which word lines are formed of a metal layer having a small sheet resistance and in which main word lines disposed over bit line layers are tapped to the cell word line.
In a conventional line layout structure having a two or three-layer metal layer, word lines are disposed in an orthogonal direction to bit lines formed of a first metal line and main word lines and power lines or signal lines formed of a second metal line are disposed in the word line direction. Further, in the line layout structure having the three-layer metal layer, power lines and signaling lines may be formed of a third metal line.
Semiconductor memory devices having the conventional line layout are not suitable for realization of a high integration semiconductor memory device since the word lines; the power lines and the signal lines are formed as metal lines of the same layer.
Further, arrangement of the power lines is an important issue when metal lines of a multi-layered structure are disposed for high performance and high integration semiconductor memory devices. That is, a noise or a drop phenomenon occurring in the power supply may reduce the performance of the semiconductor memory device.
Further, the line layout structure having a two or three-layer metal structure is not desirable problems of increase in a delay time due to parasitic capacitance, resistance and the like between upper and lower metal layers. As a result, such problems become constraints in fabricating high performance and high integration semiconductor memory devices.
Therefore, a need exists for an enhanced line layout structure in the art.